define usage in verilog and Macro

`define is very useful in verilog and here are some examples for that which will be useful to debug and develop smart macros. Simple usage of define is with ifdef and ifndef as shown . pass with compilation as  +define+XYZ `ifdef XYZ <code>  `endif   Define with some value associated with it. +define+ABC=2  Defines used…

Handling write and read file verilog

Functions used for writing and reading from file in verilog. fopen fclose fscanf  – read from file as per format fwrite – write to file as per format fdisplay -write to file Above Function are similar to C programming file handling. Difference of fwrite and fdisplay is that fwrite does not insert newline after each…

Write and Read all UVM Registers

UVM provides in built sequences to test registers like hw_reset and bit_bash . But , it is necessary to have sequence which write to all registers first and then read back.  Which will help to identify address aliasing issue. I have created uvm reg sequence which does this job. This sequence should be used same…

Packages in System Verilog

Here are some of points for packages in SV By default , if no package defined , variable will be in $unit package. It is good idea to have package which helps in code management and also for separate compilation flow. Generally Package should not have any dependency on other package or hierarchical path ,…

Response from driver to sequencer

Driver and sequencer are connected by TLM push/pull port in UVM. If driver is getting response from interface and needs to be driven to sequence then same port can be used to send response back to sequence. For that response can be sent by using  seq_item_export.put(rsp)  in driver and sequence will use get_response(rsp) . By…

Code coverage Commands with VCS , Questa and IRUN

Code coverage is used to know that how much code simulation able to cover. It is generated from simulation tool with extra arguments given. Here some of commands listed to generated code coverage by using different simulators. Add following with compile command VCS       :  -cm line+cond+fsm+tgl+branch+assert -cm_dir $(PHY_SIM_LOG).vdb Questa :  +cover=bcesxf -coveropt…

Integration Of VIP in SoC env

When you have legacy environment in pure system verilog and wants to add new VIP in UVM to that test bench then following points will help. First take reference of VIP agent example. To integrate any VIP basic steps are :  Compile and import VIP package Check all compile and run time arguments from example…

RAL model Integration in UVM

UVM RAL model is Register Abstraction Layer which simplifies register verification of ASIC. It is actually mirror image class of register module in RTL in verification environment.  It is created by using uvm_reg_field , uvm_reg, uvm_reg_block . Simulation tools available which converts IP_XACT format register description to RAL model (e.g. ralgen) . Once register model…

Multithreading and Automatic variable

Below code will explains automatic variable and multi threading. For below code , for case-1 and case-2 output is different , For case-1 output is  0 1 2 3 4 For case-2 output is 5 5 5 5 5 For case-2 it creates 2 parallel threads while for case-1 it is just initial assignment of…

Differance of FPGA and ASIC verification

 FPGA and ASIC functional verification differ majorly due to one part. It is due to its configuartion. ASIC configuration is done using register programming after reset and FPGA configuration is done using parameters. parameters needs to be passed at elaboration time. So cofiguration can not be done at run time for FPGA.So , ASIC like…

Pullup , Pulldown in verilog

For bidirectional bus mostly pullup/weak state is used on interface when no other driver is present. It can be assigned by following way. 1 . pullup(io_dq) , pulldown(io_dq) 2.  assign (weak1,weak0) io_dq = (direction) ? io : 1’bz; Below table shows different values for each strength . Strength Value Value displayed by display tasks supply…