Systemverilog assignments

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Chapter 10 in IEEE 1800-2017 gives details about assignments in system verilog.

There are mainly three types of assignments

  • Concurrent assignment :  assigning output from assign statement or assigning while declaring net . It assigns output whenever input changes value.
  • Procedural assignment : It assigns value at particular time to variable using procedural blocks like initial and always. variable holds value till it is assigned at different time.
  • Concurrent Procedural assignment :  Use of force , assign , deassign in Procedural blocks

Then , there are different ways unpacked array assignment can be done.

  • Assignment patterns :  ‘{1,2,3,4} , ‘{2{x}} . Here each item separated by comma represent single item in array
  • Unpacked array concentration : {1,2,3,4} Where each element does not necessary to be of same type as element in target array , but resultant would be of same type as target array.

Where this is nice example given to distinguish above 2 types of assignment , where last assignment is legal because resultant type same as target type.

typedef int AI3[1:3];
AI3 A3;
int A9[1:9];
A3 = ‘{1, 2, 3};
A9 = ‘{3{A3}};                     // illegal, A3 is wrong element type
A9 = ‘{A3, 4, 5, 6, 7, 8, 9}; // illegal, A3 is wrong element type
A9 = {A3, 4, 5, A3, 6}; // legal, gives A9='{1,2,3,4,5,1,2,3,6}

 

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