Passing arguments to systemverilog functions

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It is possible in systemverilog to pass default values of arguments , so that if user does not pass any arguments , it will take default value. Below is example.

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send_packet(2,3)
function void send_packet(pkt_arg1=0,pkt_arg2=0,pkt_arg3=0)

Here , pkt_arg3 will be passed as 0 .

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It is also possible to pass arguments by name using dot(.) . Below is example .

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send_packet(.pkt_arg1(2), .pkt_arg2(3))
function void send_packet(pkt_arg , pkt_arg2)

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If you use above two concepts , it is very easy to build function and use it across different classes and components . As shown below.

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  1. send_packet(.pkt_arg1(2), .pkt_arg2(3))
  2. send_packet(.pkt_arg3(4))

function void send_packet(pkt_arg1=0,pkt_arg2=0,pkt_arg3=0)

Here , send_paket is used 2 times , but both times it is using different arguments to pass .

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