Using inbuilt UVM RAL sequence

UVM RAL provides useful inbuilt sequences which can be used to verify registers .

To use these sequence environment must have integrated RAL model as per steps shown in RAL model integration

Here is list of sequence and how to use it in environment.

  • uvm_reg_bit_bash_seq :  This sequence check each register of provided RAL model by writing 1’b1 and 1’b0 to each bit of register .
  • uvm_reg_hw_reset_seq : This sequence check default value of  registers after reset.

  • uvm_reg_single_bit_bash_seq :  This is same bit bash sequence , but this sequence is used to verify one single register.
  • uvm_reg_single_all_wr_rd_seq : This is sequence developed to write all registers first and then read back all. Link for sequence

How to use : 

  1.   Create sequence  :  `uvm_create (reg_bit_bash/reg_hw_reset)
  2.   Pass register model handle :  reg_bit_bash.model = reg_model;
  3.   send sequence    :   `uvm_send (reg_bit_bash/reg_hw_reset)

To run bit bash on single register :

  1.   Create sequence  :  `uvm_create (reg_single_bit_bash)
  2.   Pass register handle :  reg_single_bit_bash.rg = reg_model.xyz_reg ;
  3.   send sequence    :   `uvm_send (reg_single_bit_bash)

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