- Three Signals : sck (clock) , sd (data) , ws (Word select)
- WS : Signal used to select Left or right audio Channel
- I2S supports only 2 channel. can be TDM used to support 4,6,8 channel using I2S interface.
TDM for Multichannel
- Same I2S interface for more than 2 channel.
- Each channel samples will be up to 32 bit time and after that next channel starts.
- Change of ws signal will determine odd/even channel. Transmitter & receiver has bit counter
AXI4 memory mapped transfer : 5 channels , AW , AR , W , B , R .
valid and ready flow to trnafer request and data. valid should not depend on ready.
AXI ID is for response reordering. So that slave can reponse to multipe requests in any order.
How address is decided :
- FIXED burst : same address
- Increment burst : start address + size*len
- For Non-modifiable burst size=size of burst(axsize) and for modifiable size=size of bus )
- if address is not aligned , then first transfer have write strobe accordingly and start address will be nearest aligned address
- WRAP burst : Increment upto address+burst*len and then WRAP to aligned address , WRAP burst always start with aligned address to size of burst.
Use of exlusive transaction :
It is used for RMW flow . For RMW transaction , Master will first do EXRD and then EXWR to same address and length . Exclusive monitor in slave will repond with response OKAY if any other master has written to that address range after EXRD.
Differance with AXI3 :
AXI3 supports upto axlen 16 while AXI4 supports upto AXLEN 256 . AXI3 had Write data interleaving support which is removed from AXI4 spec.
It has 4 interface signals . ss , sclk , miso , mosi. command starts when ss is deasserted and it is transferred from Master to slave on mosi . Slave transfers data on miso. commands are user defined.
It has two SCL , SDA bidirectional lines . It has pullup line on both signals. 1 byte is transferred at a time from Master to Slave . Then 9th bit Acknowledgement bit transferred from slave to Master. Read data stops when slave gives NACK . Slave can delay response by using clock stretching on ACK .