define usage in verilog and Macro

`define is very useful in verilog and here are some examples for that which will be useful to debug and develop smart macros.

  • Simple usage of define is with ifdef and ifndef as shown . pass with compilation as  +define+XYZ

`ifdef XYZ

<code> 

`endif

 

  • Define with some value associated with it.

+define+ABC=2 

  • Defines used as macros for repetitive code.

`define ABC(num) \

num :  abc =  xyz_“num“; 

Use in code as follows

`ABC(0)

`ABC(1)

num is integer argument passed , and to append it to string “num“ is used.

same way a string argument also can be appended.

`define ABC(string) 

  abc =  reg_“string“; 

 

 

 

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