`define is very useful in verilog and here are some examples for that which will be useful to debug and develop smart macros.
- Simple usage of define is with ifdef and ifndef as shown . pass with compilation as +define+XYZ
- Define with some value associated with it.
- Defines used as macros for repetitive code.
`define ABC(num) \
num : abc = xyz_“num“;
Use in code as follows
num is integer argument passed , and to append it to string “num“ is used.
same way a string argument also can be appended.
abc = reg_“string“;