Packages in System Verilog

Here are some of points for packages in SV

  • By default , if no package defined , variable will be in $unit package.
  • It is good idea to have package which helps in code management and also for separate compilation flow.
  • Generally Package should not have any dependency on other package or hierarchical path , If other package is required then import that package.
  • Do not include interface inside package , but it should be included in package file. e.g.

This is how ideal package file looks like.

`include “”

package x ;

`include “”

`include “”




  • package can not access variables declared in $unit package.

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