Integration Of UVM VIP

When you have legacy environment in pure system verilog and wants to add new VIP in UVM to that test bench then following points will help.

  • Passing interface to VIP agent from test bench top module using uvm_comfig_db set
  • Take configuration object of VIP in system level test and pass to VIP agent using uvm_comfig_db set 
  • Add run_test() in system verilog top module.
  • Add virtual sequencer to environment and take instance of VIP sequencer in it
  • Add system level virtual sequences which uses uvm_do_on with corresponding sequencer.
  • Pass UVM_TESTNAME from Simulation command line argument.

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