Integration Of VIP in SoC env

When you have legacy environment in pure system verilog and wants to add new VIP in UVM to that test bench then following points will help.

First take reference of VIP agent example.

To integrate any VIP basic steps are :

  1.  Compile and import VIP package
    • Check all compile and run time arguments from example and include them in Makefile at system level
    • make sure all compile warnings are resolved before running simulations
  2.   Take instance of VIP agent/env in tb_env ,  Take sequencer instance in virtual   sequencer
  3.  Pass Interface and configuration to agent by using uvm_config_db
    • Make sure all interface signals are connected properly
    • Read VIP guideline to know default value of all signals and change if it is not compatible with DUT spec.
    • Make sure reset and clock signals are connected properly and reset delay and polarity is as per spec. Clock frequency is within range of VIP and RTL.
    • Make sure VIP configuration is valid and as per VIP user guide
    • Most of problem in integration is because of configuration and interface signals connections , so make sure that they are valid
  4.  In connect_phase , connect monitor analysis port to scoreboard port if required.
  5.  In virtual sequence , start sequence of agent sequence with corresponding sequencer

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