Response from driver to sequencer

Driver and sequencer are connected by TLM push/pull port in UVM. If driver is getting response from interface and needs to be driven to sequence then same port can be used to send response back to sequence. For that response can be sent by using  seq_item_export.put(rsp)  in driver and sequence will use get_response(rsp) . By…

Code coverage Commands with VCS , Questa and IRUN

Code coverage is used to know that how much code simulation able to cover. It is generated from simulation tool with extra arguments given. Here some of commands listed to generated code coverage by using different simulators. Add following with compile command VCS       :  -cm line+cond+fsm+tgl+branch+assert -cm_dir $(PHY_SIM_LOG).vdb Questa :  +cover=bcesxf -coveropt…

Integration Of UVM VIP

When you have legacy environment in pure system verilog and wants to add new VIP in UVM to that test bench then following points will help. Passing interface to VIP agent from test bench top module using uvm_comfig_db set Take configuration object of VIP in system level test and pass to VIP agent using uvm_comfig_db…