RAL model Integration in UVM

UVM RAL model is Register Abstraction Layer which simplifies register verification of ASIC. It is actually mirror image class of register module in RTL in verification environment.  It is created by using uvm_reg_field , uvm_reg, uvm_reg_block . Simulation tools available which converts IP_XACT format register description to RAL model (e.g. ralgen) . Once register model…

Multithreading and Automatic variable

Below code will explains automatic variable and multi threading. For below code , for case-1 and case-2 output is different , For case-1 output is  0 1 2 3 4 For case-2 output is 5 5 5 5 5 For case-2 it creates 2 parallel threads while for case-1 it is just initial assignment of…

Differance of FPGA and ASIC verification

 FPGA and ASIC functional verification differ majorly due to one part. It is due to its configuartion. ASIC configuration is done using register programming after reset and FPGA configuration is done using parameters. parameters needs to be passed at elaboration time. So cofiguration can not be done at run time for FPGA.So , ASIC like…

Pullup , Pulldown in verilog

For bidirectional bus mostly pullup/weak state is used on interface when no other driver is present. It can be assigned by following way. 1 . pullup(io_dq) , pulldown(io_dq) 2.  assign (weak1,weak0) io_dq = (direction) ? io : 1’bz; Below table shows different values for each strength . Strength Value Value displayed by display tasks supply…