Unreliability Report for Coverage

Sometimes finding code coverage missing holes and root causes for that could be time consuming task. May of them conditions are not reachable by simulations as these are provided by Many simulation tools now have capability to detect unreachable conditions and exclude it automatically from coverage report. It saves lots of debug time. Following are…

vManager Notes

Below are some useful things can be done by using vManager. Automation configuration Automate merge , reporting of coverage Summary report of test and coverage at end of session export_merge database Use of batch mode for launching regression and change name of default session from command line while launching regression Rank and group testcases with…

Use of crontab for automation

when daily/weekly regressions are needed in project for some fix blocks/modules crontab are very useful. Step 1 : set cronjob using : crontab -e Example to launch regression at below time. January 2 at 6:15 A.M: 15 6 2 1 *   /home/user/launch_regression Step 2 : Make single file “launch_regression” for any block / system regression…

Use of save-restore in Simulation

Typical simulation contains initial reset sequence , bring up sequence , config sequencer for all testcases. For Regression with multiple iterations , it is not required to repeat these bring up sequence for all testcases. simulation snapshot upto one checkpoint (e.g. initialization_done) and then other iterations of testcase can run after that checkpoint. Below are…

How to use uvm_event

uvm_event is very good when you want to synchronize events between different uvm components. Also it accepts uvm_objects as arguments so that control information also can be passed between components using uvm_event. e.g. if you want some information passed from sequence to scoreboard then uvm_event can be used. How to use  ? Take new handle…

Systemverilog assignments

Chapter 10 in IEEE 1800-2017 gives details about assignments in system verilog. There are mainly three types of assignments Concurrent assignment :  assigning output from assign statement or assigning while declaring net . It assigns output whenever input changes value. Procedural assignment : It assigns value at particular time to variable using procedural blocks like…

Merging block level coverage to sytem

System level verification of SOC is complex and it covers mostly data paths and error scenarios. So code coverage of SOC will be less using only system level testbench. So to get complete idea it is usually preferred to merge block level code coverage with SOC coverage. Below is commands/ways to do it with different…

Passing arguments to systemverilog functions

It is possible in systemverilog to pass default values of arguments , so that if user does not pass any arguments , it will take default value. Below is example. ====================================== send_packet(2,3) function void send_packet(pkt_arg1=0,pkt_arg2=0,pkt_arg3=0) Here , pkt_arg3 will be passed as 0 . ====================================== It is also possible to pass arguments by name using…

Using inbuilt UVM RAL sequence

UVM RAL provides useful inbuilt sequences which can be used to verify registers . To use these sequence environment must have integrated RAL model as per steps shown in RAL model integration Here is list of sequence and how to use it in environment. uvm_reg_bit_bash_seq :  This sequence check each register of provided RAL model by…

Use of local:: scope in constraints

When using constraint , if variable name in local scope is same as random variable name in class which is randomized it results in error in constraint resolution. In this case , it is better to use local:: scope for local variables in constraints . Here is example .   Here , if local ::…

Protocol quick referance

  I2S : Three Signals : sck (clock) , sd (data) , ws (Word select) WS : Signal used to select Left or right audio Channel I2S supports only 2 channel.  can be TDM used to support 4,6,8 channel using I2S interface. TDM for Multichannel Same I2S interface for more than 2 channel. Each channel…

disable fork in SystemVerilog

If a process is started by fork .. join_any then it can be disabled by using disable fork or it can be disabled by using disable LABEL . There are some difference in using both these ways of disabling processes. Difference 1 : Here is example :   In this example , you can use disable fork or…