How to use uvm_event

uvm_event is very good when you want to synchronize events between different uvm components. Also it accepts uvm_objects as arguments so that control information also can be passed between components using uvm_event. e.g. if you want some information passed from sequence to scoreboard then uvm_event can be used. How to use  ? Take new handle…

Systemverilog assignments

Chapter 10 in IEEE 1800-2017 gives details about assignments in system verilog. There are mainly three types of assignments Concurrent assignment :  assigning output from assign statement or assigning while declaring net . It assigns output whenever input changes value. Procedural assignment : It assigns value at particular time to variable using procedural blocks like…

Merging block level coverage to sytem

System level verification of SOC is complex and it covers mostly data paths and error scenarios. So code coverage of SOC will be less using only system level testbench. So to get complete idea it is usually preferred to merge block level code coverage with SOC coverage. Below is commands/ways to do it with different…

Passing arguments to systemverilog functions

It is possible in systemverilog to pass default values of arguments , so that if user does not pass any arguments , it will take default value. Below is example. ====================================== send_packet(2,3) function void send_packet(pkt_arg1=0,pkt_arg2=0,pkt_arg3=0) Here , pkt_arg3 will be passed as 0 . ====================================== It is also possible to pass arguments by name using…

Using inbuilt UVM RAL sequence

UVM RAL provides useful inbuilt sequences which can be used to verify registers . To use these sequence environment must have integrated RAL model as per steps shown in RAL model integration Here is list of sequence and how to use it in environment. uvm_reg_bit_bash_seq :  This sequence check each register of provided RAL model by…

Use of local:: scope in constraints

When using constraint , if variable name in local scope is same as random variable name in class which is randomized it results in error in constraint resolution. In this case , it is better to use local:: scope for local variables in constraints . Here is example .   Here , if local ::…

Protocol quick referance

  I2S : Three Signals : sck (clock) , sd (data) , ws (Word select) WS : Signal used to select Left or right audio Channel I2S supports only 2 channel.  can be TDM used to support 4,6,8 channel using I2S interface. TDM for Multichannel Same I2S interface for more than 2 channel. Each channel…

disable fork in SystemVerilog

If a process is started by fork .. join_any then it can be disabled by using disable fork or it can be disabled by using disable LABEL . There are some difference in using both these ways of disabling processes. Difference 1 : Here is example :   In this example , you can use disable fork or…

define usage in verilog and Macro

`define is very useful in verilog and here are some examples for that which will be useful to debug and develop smart macros. Simple usage of define is with ifdef and ifndef as shown . pass with compilation as  +define+XYZ `ifdef XYZ <code>  `endif   Define with some value associated with it. +define+ABC=2  Defines used…

Handling write and read file verilog

Functions used for writing and reading from file in verilog. fopen fclose fscanf  – read from file as per format fwrite – write to file as per format fdisplay -write to file Above Function are similar to C programming file handling. Difference of fwrite and fdisplay is that fwrite does not insert newline after each…

Write and Read all UVM Registers

UVM provides in built sequences to test registers like hw_reset and bit_bash . But , it is necessary to have sequence which write to all registers first and then read back.  Which will help to identify address aliasing issue. I have created uvm reg sequence which does this job. This sequence should be used same…

Packages in System Verilog

Here are some of points for packages in SV By default , if no package defined , variable will be in $unit package. It is good idea to have package which helps in code management and also for separate compilation flow. Generally Package should not have any dependency on other package or hierarchical path ,…